Throughput/Area-Efficient Accelerator of Elliptic Curve Point Multiplication over GF(2233) on FPGA

This paper presents a throughput/area-efficient hardware accelerator architecture for elliptic curve point multiplication (ECPM) computation over GF(2233). The throughput of the proposed design is optimized by reducing total clock cycles using bit-parallel Karatsuba modular multiplier. We employ two techniques to minimize resources: (i) consolidated arithmetic unit where we combine single adder, multiplier, and square block instead having multiple operators, (ii) an Itoh–Tsujii inversion algorithm leveraging existing resources multiplier units multiplicative inverse computation. An efficient finite-state-machine (FSM) controller implemented facilitate control functionalities. To evaluate compare results against state-of-the-art solutions, figure-of-merit (FoM) metric in terms throughput/area defined. implementation after post-place-and-route simulation are reported reconfigurable field-programmable gate array (FPGA) devices. Particular Virtex-7 FPGA, utilizes 3584 slices, needs 7208 cycles, operates on maximum frequency 350 MHz, computes one ECPM operation 20.59 μs, calculated value FoM 13.54. Consequently, comparisons reveal that our suits applications demand area-optimized implementations.